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high performance fsk/ask transceiver ic adf7020-1 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features low power, low if transceiver frequency bands 135 mhz to 650 mhz, direct output 80 mhz to 325 mhz, divide-by-2 mode data rates supported 0.15 kbps to 200 kbps, fsk 0.15 kbps to 64 kbps, ask 2.3 v to 3.6 v power supply programmable output power ?20 dbm to +13 dbm in 63 steps receiver sensitivity ?119 dbm at 1 kbps, fsk, 315 mhz ?114 dbm at 9.6 kbps, fsk, 315 mhz ?111.8 dbm at 9.6 kbps, ask, 315 mhz low power consumption 17.6 ma in receive mode 21 ma in transmit mode (10 dbm output) on-chip vco and fractional-n pll on-chip 7-bit adc and temperature sensor fully automatic frequency control loop (afc) compensates for lower tolerance crystals digital rssi integrated trx switch leakage current <1 a in power-down mode applications low cost wireless data transfer wireless medical applications remote control/security systems wireless metering keyless entry home automation process and building control functional block diagram tx/rx control agc control fsk/ask demodulator data synchronizer rssi 7-bit adc gain div r serial port rfout offset correction offset correction lna vco pfd cp afc control osc1 osc2 dividers/ muxing n/n+1 div p mux temp sensor ring osc clk div clkout test mux vcoin cpout polarization ldo(1:4) muxout adcin rset creg(1:4) r lna rfin rfinb sle sdata ce data clk sread sclk int/lock data i/o fsk mod control gaussian filter - modulator 05669-001 if filter l1 l2 figure 1.
adf7020-1 rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications..................................................................................... 4 timing characteristics ................................................................ 8 absolute maximum ratings.......................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 typical performance characteristics ........................................... 13 frequency synthesizer ................................................................... 15 reference input........................................................................... 15 choosing channels for best system performance................. 17 transmitter ...................................................................................... 18 rf output stage.......................................................................... 18 modulation schemes.................................................................. 18 receiver section.............................................................................. 20 rf front end............................................................................... 20 rssi/agc.................................................................................... 21 fsk demodulators on the adf7020-1 ................................... 21 fsk correlator/demodulator................................................... 21 linear fsk demodulator .......................................................... 23 afc section ................................................................................ 23 automatic sync word recognition ......................................... 24 applications..................................................................................... 25 lna/pa matching...................................................................... 25 transmit protocol and coding considerations ..................... 26 device programming after initial power-up ......................... 26 interfacing to microcontroller/dsp ........................................ 26 serial interface ................................................................................ 29 readback format........................................................................ 29 register 0n register............................................................... 30 register 1oscillator/filter register...................................... 31 register 2transmit modulation register (ask/ook mode) ..................................................................... 32 register 2transmit modulation register (fsk mode) ..... 33 register 2transmit modulation register (gfsk/gook mode)................................................................ 34 register 3receiver clock register ....................................... 35 register 4demodulator set-up register.............................. 36 register 5sync byte register................................................. 37 register 6correlator/demodulator register ...................... 38 register 7readback set-up register .................................... 39 register 8power-down test register .................................. 40 register 9agc register......................................................... 41 register 10agc 2 register.................................................... 42 register 11afc register ....................................................... 42 register 12test register......................................................... 43 register 13offset removal and signal gain register ....... 44 outline dimensions ....................................................................... 45 ordering guide .......................................................................... 45 revision history 12/05revision 0: initial version
adf7020-1 rev. 0 | page 3 of 48 general description the adf7020-1 is a low power, highly integrated fsk/gfsk/ ask/ook/gook transceiver designed for operation in the low uhf and vhf bands. the adf7020-1 uses an external vco inductor that allows users to set the operating frequency anywhere between 135 mhz and 650 mhz. using the divide- by-2 circuit allows users to operate the device as low as 80 mhz. the typical range of the vco is about 10% of the operating frequency. a complete transceiver can be built using a small number of external discrete components, making the adf7020- 1 very suitable for price-sensitive and area-sensitive applications. the transmit section contains a vco and low noise fractional-n pll with output resolution of <1 ppm. this frequency agile pll allows the adf7020-1 to be used in frequency-hopping spread spectrum (fhss) systems. the vco operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. the transmitter output power is programmable in 63 steps from ?20 dbm to +13 dbm. the transceiver rf frequency, channel spacing, and modulation are programmable using a simple 3- wire interface. the device operates with a power supply range of 2.3 v to 3.6 v and can be powered down when not in use. a low if architecture is used in the receiver (200 khz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. the adf7020-1 supports a wide variety of programmable features, including rx linearity, sensitivity, and if bandwidth, allowing the user to trade off receiver sensitivity and selectivity for current consumption, depending on the application. the receiver also features a patent-pending automatic frequency control (afc) loop, allowing the pll to compensate for frequency error in the incoming signal. an on-chip adc provides readback of an integrated tempera- ture sensor, an external analog input, the battery voltage, or the rssi signal, which provides savings on an adc in some applications. the temperature sensor is accurate to 10c over the full operating temperature range of ?40c to +85c. this accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.
adf7020-1 rev. 0 | page 4 of 48 specifications v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25c. all measurements are performed using the eval-adf7020-1-dbx and pn9 data sequence, unless otherwise noted. table 1. parameter min typ max unit test conditions rf characteristics frequency ranges (direct output) 135 650 mhz see table 5 for vco bias settings at different frequencies frequency ranges (divide-by-2 mode) 80 325 mhz vco frequency range 1.1 1.2 ratio f max /f min , using vco bias settings in table 5 phase frequency detector frequency rf/256 20.96 mhz pfd must be less than direct output frequency/31 transmission parameters data rate fsk/gfsk 0.15 200 kbps ook/ask 0.15 64 1 kbps ook/ask 0.3 100 kbaud using manchester biphase-l encoding frequency shift keying gfsk/fsk frequency deviation 2 , 3 1 110 khz pfd = 3.625 mhz 4.88 620 khz pfd = 20 mhz deviation frequency resolution 100 hz pfd = 3.625 mhz gaussian filter bt 0.5 amplitude shift keying ask modulation depth 30 db ook-pa off feedthrough ?50 dbm transmit power 4 ?20 +13 dbm v dd = 3.0 v, t a = 25c, frf > 200 mhz transmit power ?20 +11 dbm v dd = 3.0 v, t a = 25c, frf < 200 mhz transmit power variation vs. temp. 1 db from ?40c to +85c transmit power variation vs. v dd 1 db from 2.3 v to 3.6 v at 315 mhz, t a = 25c programmable step size ?20 dbm to +13 dbm 0.3125 db see figure 13 for how output power varies with pa setting integer boundary ?55 dbc 50 khz loop bw reference ?65 dbc harmonics second harmonic ?27 dbc unfiltered conductive third harmonic ?21 dbc all other harmonics ?35 dbc vco frequency pulling, ook mode 30 khz rms dr = 9.6 kbps optimum pa load impedance 5 79.4 + j64 frf = 140 mhz 109 + j64 frf = 320 mhz 40 + j47.5 frf = 590 mhz
adf7020-1 rev. 0 | page 5 of 48 min typ max unit test conditions parameter receiver parameters fsk/gfsk input sensitivity at ber = 1e ? 3, frf = 315 mhz, lna and pa matched separately 6 sensitivity at 1 kbps ?119.2 dbm fdev= 5 khz, high sensitivity mode 7 sensitivity at 9.6 kbps ?114.2 dbm fdev = 10 khz, high sensitivity mode ook input sensitivity at ber = 1e ? 3, frf = 315 mhz sensitivity at 1 kbps ?118.2 dbm high sensitivity mode sensitivity at 9.6 kbps ?111.8 dbm high sensitivity mode lna and mixer, input ip3 7 enhanced linearity mode 6.8 dbm low current mode ?3.2 dbm high sensitivity mode ?35 dbm pin = ?20 dbm, 2 cw interferers, frf = 315 mhz, f1 = frf + 3 mhz, f2 = frf + 6 mhz, maximum gain rx spurious emissions 8 ?57 dbm <1 ghz at antenna input ?47 dbm >1 ghz at antenna input afc pull-in range 50 khz if_bw = 200 khz response time 48 bits modulation index = 0.875 accuracy 1 khz channel filtering adjacent channel rejection (offset = 1 if filter bw setting) 27 db second adjacent channel rejection (offset = 2 if filter bw setting) 50 db third adjacent channel rejection (offset = 3 if filter bw setting) 55 db if filter bw settings = 100 khz, 150 khz, 200 khz; desired signal 3 db above the input sensitivity level; cw interferer power level increased until ber = 10 ?3 ; image channel excluded image channel rejection 35 db image at frf ? 400 khz co-channel rejection ?2 db wideband interference rejection 70 db swept from 100 mhz to 2 ghz, measured as channel rejection blocking 1 mhz 60 db desired signal 3 db above the input sensitivity level, cw interferer power level increased until ber = 10 ?2 5 mhz 68 db 10 mhz 65 db 10 mhz (high linearity mode) 72 db saturation (maximum input level) 12 dbm fsk mode, ber = 10 ?3 lna input impedance 237 ? j193 frf = 130 mhz, rfin to gnd 101.4 ? j161.6 frf = 310 mhz 49.3 ? j104.6 frf = 610 mhz rssi range at input ?100 to ?36 dbm linearity 2 db absolute accuracy 3 db response time 150 s see the rssi/agc section
adf7020-1 rev. 0 | page 6 of 48 min typ max unit test conditions parameter phase-locked loop vco gain 40 mhz/v 433 mhz, vco adjust = 0, vco_bias_setting = 2 35 mhz/v 315 mhz, vco adjust = 0, vco_bias_setting = 2 16.5 mhz/v 135 mhz, vco adjust = 0, vco_bias_setting = 1 phase noise (in-band) ?89 dbc/hz pa = 0 dbm, v dd = 3.0 v, pfd = 10 mhz, frf = 315 mhz, vco_bias_setting = 2 normalized in-band phase noise floor 9 ?198 dbc/hz phase noise (out-of-band) ?110 dbc/hz 1 mhz offset residual fm 128 hz from 200 hz to 20 khz, frf = 315 mhz pll settling 40 s measured for a 10 mhz frequency step to within 5 ppm accuracy, pfd = 20 mhz, lbw = 50 khz reference input crystal reference 3.625 24 mhz must ensure pfd maximum is not exceeded external oscillator 3.625 24 mhz load capacitance 33 pf refer to the crystals data sheet crystal start-up time 2.1 ms 11.0592 mhz crystal, using 33 pf load capacitors 1.0 ms using 16 pf load capacitors input level cmos levels see the reference input section adc parameters inl 1 lsb from 2.3 v to 3.6 v, t a = 25c dnl 1 lsb from 2.3 v to 3.6 v, t a = 25c timing information chip enabled to regulator ready 10 s c reg = 100 nf chip enabled to rssi ready 3.0 ms see table 13 for more details tx-to-rx turnaround time 150 s + (5 t bit ) time to synchronized data out, includes agc settling. see agc information and timing section for more details. logic inputs input high voltage, v inh 0.7 v dd v input low voltage, v inl 0.2 v dd v input current, i inh /i inl 1 a input capacitance, c in 10 pf control clock input 50 mhz logic outputs output high voltage, v oh dv dd ? 0.4 v i oh = 500 a output low voltage, v ol 0.4 v i ol = 500 a clkout rise/fall 5 ns clkout load 10 pf temperature ranget a ?40 +85 c
adf7020-1 rev. 0 | page 7 of 48 min typ max unit test conditions parameter power supplies voltage supply v dd 2.3 3.6 v all v dd pins must be tied together transmit current consumption frf = 315 mhz, v dd = 3.0 v, pa is matched to 50 433 mhz, 0 dbm/5 dbm/10 dbm 13/16/21 ma vco_bias_setting = 2 receive current consumption low current mode 17.6 ma vco_bias_setting = 2 high sensitivity mode 20.1 ma vco_bias_setting = 2 power-down mode low power sleep mode 0.1 1 a 1 higher data rates are achievable, depending on local regulations. 2 for definition of frequency deviation, see the register 2transmit modulation register (fsk mode) section. 3 for definition of gfsk frequency deviation, see the register 2transmit modulation register (gfsk/gook mode) section. 4 measured as maximum unmodulated power. output power varies with both supply and temperature. 5 for matching details, see the lna/pa matching section. 6 sensitivity for combined matching network case is typically 2 db less than separate matching networks. see table 11 for sensitivity values at various data rates and frequencies. 7 see table 6 for a description of different receiver modes. 8 follow the matching and layout guidelines to achieve the relevant fcc/etsi specifications. 9 this figure can be used to calculate the in-band phase noise for any operating frequency. use the following equation to calcula te the in-band phase noise performance as seen at the pa output: C198 + 10 log( f pfd ) + 20 log n.
adf7020-1 rev. 0 | page 8 of 48 timing characteristics v dd = 3 v 10%, vgnd = 0 v, t a = 25c, unless otherwise noted. guaranteed by design, but not production tested. table 2. parameter limit at t min to t max unit test conditions/comments t 1 <10 ns sdata-to-sclk set-up time t 2 <10 ns sdata-to-sclk hold time t 3 <25 ns sclk high duration t 4 <25 ns sclk low duration t 5 <10 ns sclk-to-sle set-up time t 6 <20 ns sle pulse width t 8 <25 ns sclk-to-sread data valid, readback t 9 <25 ns sread hold time after sclk, readback t 10 <10 ns sclk-to-sle disable time, readback sclk sle db31 (msb) db30 db2 db1 (control bit c2) sdata db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 t 5 05669-002 figure 2. serial interface timing diagram t 8 t 3 t 1 t 2 t 10 t 9 x rv16 rv15 rv2 rv1 05669-003 sclk sdata sle sread reg7 db0 (control bit c1) figure 3. readback timing diagram
adf7020-1 rev. 0 | page 9 of 48 rxclk data rxdat a 1 data rate/32 1/data rate 05669-004 figure 4. rxdata/rxclk timing diagram txclk data txdat a sample fetch 1/data rate notes 1. txclk only available in gfsk mode. 05669-005 figure 5. txdata/txclk timing diagram
adf7020-1 rev. 0 | page 10 of 48 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd 1 ?0.3 v to +5 v analog i/o voltage to gnd ?0.3 v to av dd + 0.3 v digital i/o voltage to gnd ?0.3 v to dv dd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c mlf ja thermal impedance 26c/w reflow soldering peak temperature 260c time at peak temperature 40 sec 1 gnd = cpgnd = rfgnd = dgnd = agnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf-integrated circuit with an esd rating of <2 kv. it is esd sensitive; proper precautions should be taken for handling and assembly. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adf7020-1 rev. 0 | page 11 of 48 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce 48 47 46 45 44 43 42 41 40 39 38 37 cvco gnd1 l1 gnd l2 vdd cpout creg3 vdd3 osc1 osc2 muxout 1 2 3 4 5 6 7 8 9 10 11 12 vcoin creg1 vdd1 rfout rfgnd rfin rfinb r lna vdd4 rset creg4 gnd4 data clk data i/o int/lock vdd2 creg2 adcin gnd2 sclk sread sdata sle 35 clkout 36 34 33 32 31 30 29 28 27 26 25 adf7020-1 top view (not to scale) pin 1 indicator 05669-006 figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vcoin vco input pin. the tuning voltage on this pin deter mines the output frequency of the voltage controlled oscillator (vco). the higher the tuning volt age, the higher the output frequency. 2 creg1 regulator voltage for pa block. a 100 nf in parallel with a 5.1 pf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 3 vdd1 voltage supply for pa block. decoupling capacitors of 0. 1 f and 10 pf should be placed as close as possible to this pin. all v dd pins should be tied together. 4 rfout pa output pin. the modulated signal is available at this pin. output power levels are from ?20 dbm to +13 dbm. the output should be impedance matched to the desired load using suitable components. see the transmitter section. 5 rfgnd ground for output stage of transmit ter. all gnd pins should be tied together. 6 rfin lna input for receiver section. input matching is required between the antenna and the differential lna input to ensure maximum power transfer. see the lna/pa matching section. 7 rfinb complementary lna input. see the lna/pa matching section. 8 r lna external bias resistor for lna. optimum resistor is 1.1 k with 5% tolerance. 9 vdd4 voltage supply for lna/mixer block. this pin sh ould be decoupled to ground with a 10 nf capacitor. 10 rset external resistor to set charge pump current and so me internal bias currents. use 3.6 k with 5% tolerance. 11 creg4 regulator voltage for lna/mixer block. a 100 nf capaci tor should be placed between this pin and gnd for regulator stability and noise rejection. 12 gnd4 ground for lna/mixer block. 13 to 18 mix/filt signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 19, 22 gnd4 ground for lna/mixer block. filt/test_a signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 20, 21, 23 24 ce chip enable. bringing ce low puts the adf7020-1 into co mplete power-down. register values are lost when ce is low, and the part must be repr ogrammed once ce is brought high. 25 sle load enable, cmos input. when le goes high, the data st ored in the shift registers is loaded into one of the four latches. a latch is selected using the control bits. 26 sdata serial data input. the serial data is loaded msb first, with the 2 lsbs as the control bits. this pin is a high impedance cmos input.
adf7020-1 rev. 0 | page 12 of 48 mnemonic description pin no. 27 sread serial data output. this pin is used to feed readback data from the adf7020-1 to the microcontroller. the sclk input is used to clock each readback bit (afc, adc readback) from the sread pin. 28 sclk serial clock input. this serial clock is used to clock in th e serial data to the registers. the data is latched into the 24-bit shift register on the clk rising ed ge. this pin is a digital cmos input. 29 gnd2 ground for digital section. 30 adcin analog-to-digital converter input. the internal 7-bit adc can be accessed through this pin. full scale is 0 to 1.9 v. readback is made using the sread pin. 31 creg2 regulator voltage for digital block. a 100 nf in parallel wi th a 5.1 pf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 32 vdd2 voltage supply for digital block. a decoupling capacitor of 10 nf should be placed as close as possible to this pin. 33 int/lock bidirectional pin. in output mode (i nterrupt mode), the adf7020-1 asserts the int/lock pin when it has found a match for the preamble sequence. in input mode (loc k mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. once the threshold is locked, nrz data can be reliably received. in this mode, a demodula tor lock can be asserted with minimum delay. 34 data i/o transmit data input/received data output. this is a digital pin and normal cmos levels apply. 35 data clk transmit/receive clock pin. in receive mode, the pin o utputs the synchronized data clock. the positive clock edge is matched to the center of the received data. in gfsk transmit mode, the pin o utputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. see the gaussian frequency shift keying (gfsk) section. 36 clkout a divided-down version of the crystal reference with output driver. the digital clock output can be used to drive several other cmos inputs such as a microcontroller clock. the output has a 50:50 mark-space ratio. 37 muxout multiplexer output pin. this pin provides the lock_detect signal, which is used to de termine if the pll is locked to the correct frequency. other signals include regulator_re ady, which is an indicator of the status of the serial interface regulator. 38 osc2 oscillator output pin. the reference crystal should be connected between this pin and osc1. a tcxo reference can be used by driving this pin with cmos levels and disabling the crystal oscillator. 39 osc1 oscillator input pin. the reference crystal should be connected between this pin and osc2. 40 vdd3 voltage supply for the charge pump and pll dividers. this pin should be decoupled to ground with a 0.01 f capacitor. 41 creg3 regulator voltage for charge pump and pll dividers. a 100 nf in parallel with a 5.1 pf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 42 cpout charge pump output. this output genera tes current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 43 vdd voltage supply for vco tank circuit. this pin should be decoupled to ground with a 0.01 f capacitor. 44, 46 l2, l1 external vco inductor pins. a chip inductor should be connected across these pins to set the vco operating frequency. see the voltage controlled oscillator (vco) section for details on choosing the appropriate value. 45, 47 gnd, gnd1 grounds for vco block. 48 cvco vco noise compensation node. a 22 nf capacitor should be placed between this pin and creg1 to reduce vco noise.
adf7020-1 rev. 0 | page 13 of 48 typical performance characteristics 05669-007 10mhz 10.0000khz ?87.80dbc/hz carrier powe r ? 0.28dbm atten 0.00db mkr1 ref ?70.00dbc/hz 10.00 db/ 1khz frequency offset 1 figure 7. phase noise response at 315 mhz, v dd = 3.0 v, icp = 1.5 ma 05669-058 span 400 khz ref 20dbm norm log 10 db/ center 415.000 0 mhz sweep 5.359 s (601pts) vbw 300 hz #res bw 300 hz lgav v1 v2 s3 fc aa (f): f>50k swp atten 30db fsk gfsk figure 8. output spectrum in fsk and gfsk modulation 05669-009 if freq (khz) 600 ?400 ?300 ?200 ?100 0 100 200 300 400 500 550 ?350 ?250 ?150 ?50 50 150 250 350 450 attenuation level (db) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 200khz filter bw 100khz filter bw 150khz filter bw figure 9. if fi lter response 05669-010 stop 10.000ghz sweep 16.52ms (601pts) mkr4 3.482ghz sweep 16.52ms (601pts) start 100mh z res bw 3mhz ref 10dbm pea k log 10db/ vbw 3mhz atten 20db 1 3 4 ref level 10.00dbm figure 10. harmonic response, rf out matched to 50 , no filter 05669-011 stop 5.000ghz sweep 5.627s (601pts) mkr1 1.834ghz ?62.57db start 800mhz #res bw 30khz ref 15dbm atten 30db vbw 30khz norm log 10db/ lgav w1 s2 s3 fc aa (f): ftun swp 1r 1 marker 1.834000000ghz ?62.57db figure 11. harmonic response, murata dielectric filter 05669-059 span 300 khz ref 20dbm norm log 10 db/ center 415.000 0 mhz sweep 2.791 s (601pts) vbw 360 hz #res bw 360 hz lgav v1 v2 s3 fc aa (f): f>50k swp atten 30db ask ook gook figure 12. output spectrum in ask, oo k, and gook modes, dr = 10 kbps
adf7020-1 rev. 0 | page 14 of 48 05669-013 pa setting 1 5 9 13172125293337414549535761 pa output power 20 10 15 0 5 ?10 ?5 ?20 ?15 ?25 11 a 9 a 5 a 7 a figure 13. pa output power vs. setting 05669-057 10mhz 10.0000khz ?86.20dbc/hz carrier power 10.75dbm atten 6.00db mkr1 ref ?70.00dbc/hz 10.00 db/ 1khz frequency offset figure 14. wideband interference rejection. wanted signal (880 mhz) at 3 db above sensitivity point interferer = fm jammer (9.76 kbps, 10k deviation) 05669-015 20 ?120 ?100 ?80 ?60 ?40 ?20 0 20 ?20 ?60 0 ?40 ?80 ?100 ?120 actual input level rssi readback level rf i/p (db) rssi level (db) figure 15. digital rssi readback linearity ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 log (ber) +2.3v,+85c ?127 ?126 ?125 ?124 ?123 ?122 ?121 ?120 ?119 ?118 ?117 ?116 ?115 input power (dbm) 05669-016 +2.3v,+25c +3.6v,+85c +3.6v,+25c +2.3v,?40c +3.6v,?40c +3.0v,?40c figure 16. sensitivity vs. v dd and temperature, rf = 315 mhz, dr = 1 kbps, correlator demod 05669-017 rf i/p level (dbm) ?90 ?122 ?121 ?120 ?119 ?118 ?117 ?116 ?115 ?114 ?113 ?112 ?111 ?110 ?109 ?108 ?107 ?106 ?105 ?104 ?103 ?102 ?101 ?100 ?99 ?98 ?97 ?96 ?95 ?94 ?93 ?92 ?91 ber 0 ?1 ?2 ?4 ?5 ?3 ?6 ?7 ?8 9.760k data rate 200.8k data rate 1.002k data rate figure 17. ber vs. data-rate (combine d matching network) separate lna and pa matching paths typically improve performance by 2 db 05669-018 frequency error (khz) 110 ?110 ?90 ?70 ?50 ?30 ?10 10 30 50 70 90 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 rf i/p level (dbm) ?60 ?70 ?75 ?65 ?80 ?85 ?90 ?95 ?100 ?105 ?110 linear afc off linear afc on correlation afc on correlation afc off figure 18. sensitivity vs. frequency error with afc on/off
adf7020-1 rev. 0 | page 15 of 48 frequency synthesizer reference input the on-board crystal oscillator circuitry (see figure 19 ) can use an inexpensive quartz crystal as the pll reference. the oscil- lator circuit is enabled by setting r1_db12 high. it is enabled by default on power-up and is disabled by bringing ce low. errors in the crystal can be corrected using the automatic frequency control (see the afc section ) feature or by adjusting the fractional-n value (see the n counter section). a single-ended reference (tcxo, cxo) can also be used. the cmos levels should be applied to osc2 with r1_db12 set low. osc1 cp1 cp2 osc2 5669-019 figure 19. oscillator circuit on the adf7020-1 two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. they should be chosen so that the series value of capacitance added to the pcb track capacitance adds up to the load capacitance of the crystal, usually 20 pf. track capacitance values vary from 2 pf to 5 pf, depending on board layout. where possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. clkout divider and buffer the clkout circuit takes the reference clock signal from the oscillator section (see figure 19 ) and supplies a divided-down 50:50 mark-space signal to the clkout pin. an even divide from 2 to 30 is available. this divide number is set in r1_db (8:11). on power-up, the clkout defaults to the divide-by-8 block. dv dd clkout enable bit clkout osc1 divider 1 to 15 05669-020 2 figure 20. clkout stage to disable clkout, set the divide number to 0. the output buffer can drive up to a 20 pf load with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at f clk . r counter the 3-bit r counter divides the reference input frequency by an integer from 1 to 7. the divided-down signal is presented as the reference clock to the phase frequency detector (pfd). the divide ratio is set in register 1. maximizing the pfd frequency reduces the n value. this reduces the noise multiplied at a rate of 20 log(n) to the output, as well as reducing occurrences of spurious components. the r register defaults to r = 1 on power-up: pfd [hz] = xtal/r muxout and lock detect the muxout pin allows the user to access various digital points in the adf7020-1. the state of muxout is controlled by bits r0_db (29:31). regulator ready regulator ready is the default setting on muxout after the transceiver has been powered up. the power-up time of the regulator is typically 50 s. because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the adf7020-1 can be programmed. the status of the regulator can be monitored at muxout. when the regulator ready signal on muxout is high, programming of the adf7020-1 can begin. regulator ready digital lock detect analog lock detect r counter output n counter output pll test modes - test modes mux control dgnd dv dd muxout 05669-021 figure 21. muxout circuit digital lock detect digital lock detect is active high. the lock detect circuit is located at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until 25 ns phase error is detected at the pfd. because no external components are needed for digital lock detect, it is more widely used than analog lock detect.
adf7020-1 rev. 0 | page 16 of 48 analog lock detect this n-channel, open-drain lock detect should be operated with an external pull-up resistor of 10 k nominal. when a lock has been detected, this output is high with narrow low-going pulses. voltage regulators the adf7020-1 contains four regulators to supply stable voltages to the part. the nominal regulator voltage is 2.3 v. each regulator should have a 100 nf capacitor connected between creg and gnd. when ce is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 ma. bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 a, and erases all values held in the registers. the serial interface operates from a regulator supply; therefore, to write to the part, the user must have ce high and the regulator voltage must be stabilized. regulator status (creg4) can be monitored using the regulator ready signal from muxout. loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop-filter design is shown in figure 22 . 05669-022 charge pump out vco figure 22. typical loop-filter configuration in fsk, the loop should be designed so that the loop bandwidth (lbw) is approximately 5 times the data rate. widening the lbw excessively reduces the time spent jumping between frequencies, but can cause insufficient spurious attenuation. for ask systems, a wider lbw is recommended. the sudden large transition between two power levels might result in vco pulling and can cause a wider output spectrum than is desired. by widening the lbw to more than 10 times the data rate, the amount of vco pulling is reduced, because the loop settles quickly back to the correct frequency. the wider lbw might restrict the output power and data rate of ask-based systems more than it would that of fsk-based systems. narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. careful design of the loop filter is critical to obtaining accurate fsk/gfsk modulation. for gfsk, it is recommended that an lbw of 2.0 to 2.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. the free design tool adisimpll can be used to design loop filters for the adf7020-1. n counter the feedback divider in the adf 7020-1 pll consists of an 8-bit integer counter and a 15-bit - fractional-n divider. the integer counter is the standard pulse-swallow type common in plls. this sets the minimum integer divide value to 31. the fractional divide value gives very fine resolution at the output, where the output frequency of the pll is calculated as ) 2 ( 15 n fractional ninteger r xtal f out ? +?= 05669-023 vco 4\n third-order - modulator pfd/ charge pump 4\r integer-n fractional-n reference in figure 23. fractional-n pll the combination of the integer-n (maximum = 255) and the fractional-n (maximum = 16,383/16,384) give a maximum n divider of 255 + 1. therefore, the minimum usable pfd is pfd min [hz] = maximum required output frequency /(255 + 1) for example, when operating at 620 mhz, pfd min equals 2.42 mhz. voltage controlled oscillator (vco) the adf7020-1 features an on-chip vco with external tank inductor, which is used to set the frequency range. the center frequency of the vco is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and pcb track. a plot of vco operating range vs. total external inductance (chip inductor + pcb track) is shown in figure 24 . the inductance for a pcb track using fr4 material is approximately 0.57 nh/mm. this should be subtracted from the total value to determine the correct chip inductor value. an additional frequency divide-by-2 block is included to allow operation from 80 mhz to 325 mhz. to enable the divide-by-2 block, set r1_db13 to 1.
adf7020-1 rev. 0 | page 17 of 48 the vco can be recentered, depending on the required frequency of operation, by programming the vco adjust bits r1_db (20:21). choosing channels for best system performance the fractional-n pll allows the selection of any channel within 80 mhz to 650 mhz to a resolution of <300 hz. this also facilitates frequency-hopping systems. the vco is enabled as part of the pll by the pll-enable bit, r0_db28. careful selection of the rf transmit channels must be made to achieve best spurious performance. the architecture of fractional-n results in some level of the nearest integer channel moving through the loop to the rf output. these beat-note spurs are not attenuated by the loop if the desired rf channel and the nearest integer channel are separated by a frequency of less than the lbw. the vco needs an external 22 nf between the vco and the regulator to reduce internal noise. 05669-024 0 5 10 15 20 25 30 200 250 300 350 400 450 500 550 600 650 700 total external inductance (nh) frequency (mhz) 750 f min (mhz) f max (mhz) the occurrence of beat-note spurs is rare, because the integer frequencies are at multiples of the reference, which is typically >10 mhz. the amplitude of beat-note spurs can be significantly reduced by using the frequency doubler to avoid very small or very large values in the fractional register. by having a channel 1 mhz away from an integer frequency, a 100 khz loop filter can reduce the level to 450 mhz 0011 vco loop filter mux vco select bit to pa vco bias r1_db (16:19) 220 f 05669-025 cvco pin 2 2 to n divider figure 25. voltage controlled oscillator (vco)
adf7020-1 rev. 0 | page 18 of 48 transmitter rf output stage the pa of the adf7020-1 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dbm into a 50 load at a maximum frequency of 650 mhz. the pa output current and, consequently, the output power are programmable over a wide range. the pa configurations in fsk/gfsk and ask/ook modulation modes are shown in figure 26 and figure 27 , respectively. in fsk/gfsk modulation mode, the output power is independent of the state of the data_io pin. in ask/ook modulation mode, it is dependent on the state of the data_io pin and bit r2_db29, which selects the polarity of the txdata input. for each transmission mode, the output power can be adjusted as follows: ? fsk/gfsk: the output power is set using bits r2_db (9:14). ? ask: the output power for the inactive state of the txdata input is set by bits r2_db (15:20). the output power for the active state of the txdata input is set by bits r2_db (9:14). ? ook: the output power for the active state of the txdata input is set by bits r2_db (9:14). the pa is muted when the txdata input is inactive. idac 2 6 r2_db(9:14) r2_db4 r2_db5 digital lock detect r2_db(30:31) + rfgnd rfout from vco 05669-026 figure 26. pa configuration in fsk/gfsk mode idac r2_db(9:14) r2_db(15:23) r2_db4 r2_db5 digital lock detect r2_db(30:31) r2_db29 + rfgnd rfout from vco 05669-027 6 6 6 0 ask/ook mode data i/ o figure 27. pa configuration in ask/ook mode the pa is equipped with overvoltage protection, which makes it robust in severely mismatched conditions. depending on the application, users can design a matching network for the pa to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or mono- pole antennas. see the lna/pa matching section for details. pa bias currents control bits r2_db (30:31) facilitate an adjustment of the pa bias current to further extend the output power control range, if necessary. if this feature is not required, the default value of 9 a is recommended. the output stage is powered down by resetting bit r2_db4. to reduce the level of undesired spurious emissions, the pa can be muted during the pll lock phase by toggling this bit. modulation schemes frequency shift keying (fsk) frequency shift keying is implemented by setting the n value for the center frequency and then toggling this with the txdata line. the deviation from the center frequency is set using bits r2_db (15:23). the deviation from the center frequency in hertz is 14 2 hz][ number m odulation pfd fsk deviation = where modulation number is a number from 1 to 511 (r2_db (15:23)). select fsk using bits r2_db (6:8). 05669-028 vco n third-order - modulator pfd/ charge pump 4r integer-n fractional-n pa stage ?f dev +f dev txdata fsk deviation frequency figure 28. fsk implementation
adf7020-1 rev. 0 | page 19 of 48 gaussian frequency shift keying (gfsk) amplitude shift keying (ask) gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the txdata. a txclk output line is provided from the adf7020-1 for synchronization of txdata from the micro- controller. the txclk line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate. amplitude shift keying is implemented by switching the output stage between two discrete power levels. this is accomplished by toggling the dac, which controls the output level between two 6-bit values set up in register 2. a 0 txdata bit sends bits r2_db (15:20) to the dac. a high txdata bit sends bits r2_db (9:14) to the dac. a maximum modulation depth of 30 db is possible. on-off keying (ook) setting up the adf7020-1 for gfsk on-off keying is implemented by switching the output stage to a certain power level for a high txdata bit and switching the output stage off for a low txdata bit. for ook, the transmitted power for a high input is programmed using bits r2_db (9:14). to set up the frequency deviation, set the pfd and the modulator control bits according to the following equation: 12 2 2 ]hz[ m deviation pfd gfsk = gaussian on-off keying (gook) gaussian on-off keying represents a prefiltered form of ook modulation. the usually sharp symbol transitions are replaced with smooth gaussian filtered transitions, the result being a reduction in frequency pulling of the vco. frequency pulling of the vco in ook mode can lead to a wider than desired bw, especially if it is not possible to increase the loop-filter bw > 300 khz. the gook sampling clock samples data at the data rate. (see the setting up the adf7020-1 for gfsk section.) where m is gfsk_mod_control set using r2_db (24:26). to set up the gfsk data rate, set the pfd and the modulator control bits according to the following equation: counter index factor divider pfd dr _ _ ]bps[ = where divider_factor and index_counter are programmed in bits r2_db (15:21) and r2_db (27:28), respectively. for further information, see the using gfsk on the adf7010 section in the eval-adf7010eb1 data sheet.
adf7020-1 rev. 0 | page 20 of 48 receiver section rf front end the adf7020-1 is based on a fully integrated, low if receiver architecture. the low if architecture facilitates a very low external component count and does not suffer from power-line- induced interference problems. figure 29 shows the structure of the receiver front end. the many programming options allow users to trade off sensitivity, linearity, and current consumption for each other in the most suitable way for their applications. to achieve a high level of resilience against spurious reception, the lna features a differential input. switch sw2 shorts the lna input when transmit mode is selected (r0_db27 = 0). this feature facili- tates the design of a combined lna/pa matching network, avoiding the need for an external rx/tx switch. see the lna/pa matching section for details on the design of the matching network. 05669-029 sw2 lna rfin rfinb t x/rx select [r0_db27] lna mode [r6_db15] lna current [r6_db(16:17)] mixer linearity [r6_db18] lo i (to filter) q (to filter) lna gain [r9_db(20:21)] lna/mixer enable [r8_db6] figure 29. adf7020-1 rf front end the lna is followed by a quadrature down conversion mixer, which converts the rf signal to the if frequency of 200 khz. it is important to consider that the output frequency of the syn- thesizer must be programmed to a value 200 khz below the center frequency of the received channel. the lna has two basic operating modes: high gain/low noise mode and low gain/low power mode. to switch between these two modes, use the lna_mode bit, r6_db15. the mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, r6_db18. based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits lna_mode (r6_db15) and mixer_linearity (r6_db18) as outlined in tabl e 6 . the gain of the lna is configured by the lna_gain field, r9_db (20:21), and can be set by either the user or the automatic gain control (agc) logic. if filter settings/calibration out-of-band interference is rejected by means of a fourth-order butterworth polyphase if filter centered around a frequency of 200 khz. the bandwidth of the if filter can be programmed between 100 khz and 200 khz by means of control bits r1_db (22:23); it should be chosen as a compromise between inter- ference rejection, attenuation of the desired signal, and the afc pull-in range. to compensate for manufacturing tolerances, the if filter should be calibrated once after power-up. the if filter calibration logic requires that the if filter divider in bits r6_db (20:28) be set dependent on the crystal frequency. once initiated by setting bit r6_db19, the calibration is performed automatically without any user intervention. the calibration time is 200 s, during which the adf7020-1 should not be accessed. it is important not to initiate the calibration cycle before the crystal oscillator has fully settled. if the agc loop is disabled, the gain of if filter can be set to three levels using the filter_gain field, r9_db (22:23). the filter gain is adjusted automatically, if the agc loop is enabled. table 6. lna/mixer modes receiver mode lna mode (r6_db15) lna gain value r9_db (21:20) mixer linearity (r6_db18) sensitivity (dr = 9.6 kbps, f dev = 10 khz) rx current consumption (ma) input ip3 (dbm) high sensitivity mode (default) 0 30 0 ?112.5 20.1 ?35 rxmode2 1 10 0 ?105.8 19.0 ?15.9 low current mode 1 3 0 ?92.2 17.6 ?3.2 enhanced linearity mode 1 3 1 ?102.5 17.6 +6.8 rxmode5 1 10 1 ?99 19.0 ?8.25 rxmode6 0 30 1 ?105 20.1 ?28.8
adf7020-1 rev. 0 | page 21 of 48 rssi/agc the rssi is implemented as a successive compression log amp following the base-band channel filtering. the log amp achieves 3 db log linearity. it also doubles as a limiter to convert the signal-to-digital levels for the fsk demodulator. the rssi itself is used for amplitude shift keying (ask) demodulation. in ask mode, extra digital filtering is performed on the rssi value. offset correction is achieved using a switched capacitor integra- tor in feedback around the log amp. this uses the bb offset clock divide. the rssi level is converted for user readback and digitally controlled agc by an 80-level (7-bit) flash adc. this level can be converted to input power in dbm. 1 ifwr ifwr ifwr ifwr latch aaa r clk adc offset correction rssi ask demod fsk demod 05669-030 figure 30. rssi block diagram rssi thresholds when the rssi is above agc_high_threshold, the gain is reduced. when the rssi is below agc_low_threshold, the gain is increased. a delay (agc_delay) is programmed to allow for settling of the loop. the user programs the two threshold values (recommended defaults, 30 and 70) and the delay (default, 10). the default agc set-up values should be adequate for most applications. the threshold values must be more than 30 settings apart for the agc to operate correctly. offset correction clock in register 3, the user should set the bb offset clock divide bits r3_db (4:5) to give an offset clock between 1 mhz and 2 mhz, where: bbos_clk (hz) = xtal /( bbos_clk_divide ) bbos_clk_divide can be set to 4, 8, or 16. agc information and timing agc is selected by default, and operates by selecting the appro- priate lna and filter gain settings for the measured rssi level. it is possible to disable agc by writing to register 9 if you want to enter one of the modes listed in tabl e 6 , for example. the time for the agc circuit to settle and hence the time it takes to take an accurate rssi measurement is typically 150 s, although this depends on how many gain settings the agc circuit has to cycle through. after each gain change, the agc loop waits for a programmed time to allow transients to settle. this wait time can be adjusted to speed up this settling by adjusting the appropriate parameters. xtal divide clkseq delay agc timewaitagc __ _ __ = agc settling = agc_wait_time number of gain changes thus, in the worst case, if the agc loop has to go through all five gain changes, agc delay = 10, and seq_clk = 200 khz, then agc settling = 10 5 s 5 = 250 s. minimum agc_wait_time must be at least 25 s. rssi formula (converting to dbm) inputpower [dbm] = ?120 dbm + ( readback_code + gain_mode_correction ) 0.5 where: readback_code is given by bits rv7 to rv1 in the readback register (see readback format section). gain_mode_correction is given by the values in tabl e 7 . lna gain and filter gain (lg2/lg1, fg2/fg1) are also obtained from the readback register. table 7. gain mode correction lna gain (lg2, lg1) filter gain (fg2, fg1) gain mode correction h (1, 1) h (1, 0) 0 m (1, 0) h (1, 0) 24 m (1, 0) m (0, 1) 45 m (1, 0) l (0, 0) 63 l (0, 1) l (0, 0) 90 el (0, 0) l (0, 0) 105 an additional factor should be introduced to account for losses in the front-end matching network/antenna. fsk demodulators on the adf7020-1 the two fsk demodulators on the adf7020-1 are ? fsk correlator/demodulator ? linear demodulator select these using the demodulator select bits, r4_db (4:5). fsk correlator/demodulator the quadrature outputs of the if filter are first limited and then fed to a pair of digital frequency correlators that perform band- pass filtering of the binary fsk frequencies at (if + f dev ) and (if ? f dev ). data is recovered by comparing the output levels from each of the two correlators. the performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of awgn.
adf7020-1 rev. 0 | page 22 of 48 post demod filter data synchronizer if ? f dev if + f dev i if q limiters 0 db(4:13) db(8:15) db(14) rx data rx clk slicer frequency correlator 05669-031 figure 31. fsk correlator/demodulator block diagram postdemodulator filter a second-order digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. the bandwidth of this postdemodulator filter is programmable and must be optimized for the users data rate. if the bandwidth is set too narrow, performance is degraded due to intersymbol interference (isi). if the bandwidth is set too wide, excess noise degrades the receivers performance. typically, the 3 db bandwidth of this filter is set at approximately 0.75 times the users data rate, using bits r4_db (6:15). bit slicer the received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. in the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on zero. therefore, the slicer threshold level can be fixed at zero, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. this results in robust data recovery, which does not suffer from the classic baseline wander prob- lems that exist in the more traditional fsk demodulators. frequency errors are removed by an internal afc loop that measures the average if frequency at the limiter output and applies a frequency correction value to the fractional-n synthesizer. this loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation (see the afc section ). data synchronizer an oversampled digital pll is used to resynchronize the received bit stream to a local clock. the oversampled clock rate of the pll (cdr_clk) must be set at 32 times the data rate. see the notes for the register 3receiver clock register section for a definition of how to program the various on-chip clocks. the clock recovery pll can accommodate frequency errors of up to 2%. fsk correlator register settings to enable the fsk correlator/demodulator, bits r4_db (5:4) should be set to [01]. to achieve best performance, the bandwidth of the fsk correlator must be optimized for the specific deviation frequency that is used by the fsk transmitter. the discriminator bw is controlled in register 6 by r6_db (4:13) and is defined as )10800/()_(_ 3 = kclk demod bwtor discrimina where: demod_clk is as defined in the register 3receiver clock register section, note 2. k = round(200e3/fsk deviation) to optimize the coefficients of the fsk correlator, two additional bits, r6_db14 and r6_db29, must be assigned. the value of these bits depends on whether k (as defined above) is odd or even. these bits are assigned according to the conditions listed in tabl e 8 and tabl e 9 . table 8. when k is even k k/2 r6db14 r6db29 even even 0 0 even odd 0 1 table 9. when k is odd k k 1/2 r6db14 r6db29 odd even 1 0 odd odd 1 1 postdemodulator bandwidth register settings the 3 db bandwidth of the postdemodulator filter is controlled by bits r4_ db (6:15) and is given by clk demod f setting bw demod post cutoff _ 22 ___ 10 = where f cutoff is the target 3 db bandwidth in hertz of the post- demodulator filter. this should typically be set to 0.75 times the data rate (dr). some sample settings for the fsk correlator/demodulator are demod_clk = 5 mhz dr = 9.6 kbps f dev = 20 khz therefore f cutoff = 0.75 9.6 10 3 hz post_demod_bw = 2 11 7.2 10 3 hz/(5 mhz) post_demod_bw = round (9.26) = 9 and k = round (200 khz)/20 khz) = 10 discriminator_bw = (5 mhz 10)/(800 10 3 ) = 62.5 = 63 (rounded to nearest integer) table 10. register settings setting name register address value post_demod_bw r4_db (6:15) 0x09 discriminator_bw r6_db (4:13) 0x3f dot product r6_db14 0 rx data invert r6_db29 1
adf7020-1 rev. 0 | page 23 of 48 linear fsk demodulator figure 32 shows a block diagram of the linear fsk demodulator. averaging filter envelope detector slicer frequency if level i q limiter 7 mux 1 adc rssi output linear discriminator db(6:15) frequency readback and afc loop rx data 05669-032 figure 32. block diagram of frequency measurement system and ask/ook/linear fsk demodulator this method of frequency demodulation is useful when very short preamble length is required and the system protocol cannot support the overhead of the settling time of the internal feedback afc loop settling. a digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. the discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. the demodu- lated fsk data is recovered by comparing the filter output with its average value, as shown in figure 32 . in this mode, the slicer output shown in figure 32 is routed to the data synchronizer pll for clock synchronization. to enable the linear fsk demodulator, set bits r4_db (4:5) to [00]. the 3 db bandwidth of the postdemodulation filter is set in the same way as the fsk correlator/demodulator, which is set in r4_db (6:15) and is defined as clk demod f setting bw demod post cutoff _ 22 ___ 10 = where: f cutoff is the target 3 db bandwidth in hertz of the postdemodulator filter. demod_clk is as defined in the register 3receiver clock register section, note 2. ask/ook operation ask/ook demodulation is activated by setting bits r4_db (4:5) to [10]. ask/ook demodulation is performed by digitally filtering the rssi output, and then comparing the filter output with its average value in a similar manner to fsk demodulation. the bandwidth of the digital filter must be optimized to remove any excess noise without causing isi in the received ask/ook signal. the 3 db bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by r4 _db (6:15) as post_demod_bw_setting = demod_clk f cutoff 22 10 where f cutoff is the target 3 db bandwidth in hertz of the postdemodulator filter. it is also recommended to use manchester encoding in ask/ook mode to ensure the data run length limit (rll) is 2 bits. if a longer rll, up to a maximum of 4 bits, is required, users should disable the extra-low gain setting by writing 0x3c00c to the test mode register. afc section the adf7020-1 supports a real-time afc loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. the afc loop uses the frequency discriminator block as described in the linear fsk demodulator section (see figure 32 ). the discriminator output is filtered and averaged to remove the fsk frequency modulation using a combined averaging filter and envelope detector. in fsk mode, the output of the envelope detector provides an estimate of the average if frequency. two methods of afc, external and internal, are supported on the adf7020-1 (in fsk mode only). external afc the user reads back the frequency information through the adf7020-1 serial port and applies a frequency correction value to the fractional-n synthesizers n divider. the frequency information is obtained by reading the 16-bit signed afc_readback, as described in the readback format section, and applying the following formula: freq_rb [hz] = ( afc_readback demod_clk )/2 15 note that while the afc_readback value is a signed number, under normal operating conditions it is positive. in the absence of frequency errors, the freq_rb value is equal to the if frequency of 200 khz. internal afc the adf7020-1 supports a real-time internal automatic fre- quency control loop. in this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer n divider using an internal pi control loop. the internal afc control loop parameters are controlled in register 11. the internal afc loop is activated by setting r11_db20 to 1. a scaling coefficient must also be entered, based on the crystal frequency in use. this is set up in r11_db (4:19) and should be calculated using afc_scaling_coefficient = (500 2 24 )/ xtal therefore, using a 10 mhz xtal yields an afc scaling coefficient of 839.
adf7020-1 rev. 0 | page 24 of 48 afc performance the improved sensitivity performance of the rx when afc is enabled and in the presence of frequency errors is shown in figure 18 . the maximum afc pull-in range is 50 khz, which corresponds to 58 ppm at 868 mhz. this is the total error tolerance allowed in the link. for example, in a point-to-point system, afc can compensate for two 29 ppm crystals or one 50 ppm crystal and one 8 ppm tcxo. afc settling typically takes 48 bits to settle within 1 khz. this can be improved by increasing the postdemodulator bandwidth in register 4 at the expense of rx sensitivity. when afc errors have been removed using either the internal or external afc, further improvement in the receivers sensitivity can be obtained by reducing the if filter bandwidth using bits r1_db (22:23). automatic sync word recognition the adf7020-1 also supports automatic detection of the sync or id fields. to activate this mode, the sync (or id) word must be preprogrammed in the adf7020-1. in receive mode, this preprogrammed word is compared to the received bit stream, and the external pin int/lock is asserted by the adf7020-1 when a valid match is identified. this feature can be used to alert the microprocessor that a valid channel has been detected. it relaxes the computational require- ments of the microprocessor and reduces the overall power consumption. the int/lock is automatically deasserted again after nine data clock cycles. the automatic sync/id word detection feature is enabled by selecting demodulator mode 2 or 3 in the demodulator set-up register. do this by setting r4_db (25:23) = [010] or [011]. bits r5_db (4:5) are used to set the length of the sync/id word, which can be 12, 16, 20, or 24 bits long. the transmitter must transmit the msb of the sync byte first and the lsb last to ensure proper alignment in the receiver sync byte detection hardware. for systems using fec, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. the error tolerance value is assigned in r5_db (6:7). table 11. sensitivity values for varying rf frequency and data rates frequency data rate (nrz) deviation in fsk mode fsk sensitivity at ber = 1e-3, correlator demodulator fsk sensitivity at ber = 1e-3, linear demodulator ask sensitivity at ber = 1e-3 135 mhz 9.6 kbps 10 khz ?113.2 dbm ?106.2 dbm ?110.8 135 mhz 1.0 kbps 5 khz ?119.5 dbm ?109.2 dbm ?116.8 dbm 315 mhz 9.6 kbps 10 khz ?114.2 dbm ?108.0 dbm ?111.8 dbm 315 mhz 1.0 kbps 5 khz ?120 dbm ?110.1 dbm ?118 dbm 610 mhz 9.6 kbps 10 khz ?113.2 dbm ?107.0 dbm ?110.5 dbm 610 mhz 1.0 kbps 5 khz ?119.8 dbm ?109.0 dbm ?116.8 dbm
adf7020-1 rev. 0 | page 25 of 48 applications lna/pa matching the adf7020-1 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its rf input and output ports are properly matched to the antenna impedance. for cost-sensitive applications, the adf7020-1 is equipped with an internal rx/tx switch, which facilitates the use of a simple combined passive pa/lna matching network. alternatively, an external rx/tx switch, such as the analog devices adg919, can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. external rx/tx switch figure 33 shows a configuration using an external rx/tx switch. this configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is therefore more flexible and less difficult to design than the configuration using the internal rx/tx switch. the pa is biased through inductor l1, and c1 blocks the dc current. both elements, l1 and c1, also form the matching network, which transforms the source impedance into the optimum pa load impedance, z opt _pa. 05669-033 pa lna pa_out rfin rfinb v bat l1 adf7020-1 adg919 optional bpf (saw) optional lpf l a c a c b z in _rfin z opt _pa z in _rfin antenna rx/tx ? select figure 33. adf7020-1 with external rx/tx switch z opt _pa depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. selecting an appropriate z opt _pa helps to minimize the tx current consumption in the application. the specifications section lists a number of z opt _pa values for representative conditions. under certain conditions, however, it is recommended to obtain a suitable z opt _pa value by means of a load-pull measurement. due to the differential lna input, the lna matching network must be designed to provide both a single-ended to differential conversion and a complex conjugate impedance match. the network with the lowest component count that can satisfy these requirements is the configuration shown in figure 33 , which consists of two capacitors and one inductor. a first-order implementation of the matching network can be obtained by understanding the arrangement as two l type matching networks in a back-to-back configuration. due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the lna input must be established. the use of appropriate cad software is strongly recommended for this optimization. depending on the antenna configuration, the user might need a harmonic filter at the pa output to satisfy the spurious emission requirement of the applicable government regulations. the harmonic filter can be implemented in various ways, such as a discrete lc pi or t-stage filter. the immunity of the adf7020-1 to strong out-of-band interference can be improved by adding a band-pass filter in the rx path, or alternatively by selecting one of the high linearity modes outlined in table 6 . internal rx/tx switch figure 34 shows the adf7020-1 in a configuration where the internal rx/tx switch is used with a combined lna/pa matching network. this is the configuration used in the adf7020-1dbx evaluation boards. for most applications, the slight performance degradation of 1 db to 2 db caused by the internal rx/tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. the design of the combined matching network must compensate for the reactance presented by the networks in the tx and the rx paths, taking the state of the rx/tx switch into consideration. 05669-034 pa lna pa_out rfin rfinb v bat l1 adf7020-1 optional bpf or lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin a ntenn a figure 34. adf7020-1 with internal rx/tx switch the procedure typically requires several iterations until an acceptable compromise is reached. the successful implementation of a combined lna/pa matching network for the adf7020-1 is critically dependent on the availability of an accurate electrical model for the pc board. in this context, the use of a suitable cad package is strongly recommended. to avoid this effort, however, a small form-factor reference design for the adf7020-1 is provided, including matching and harmonic filter components. the design is on a 2-layer pcb to minimize cost. gerber files are available on the www.analog.com website.
adf7020-1 rev. 0 | page 26 of 48 transmit protocol and coding considerations interfacing to microcontroller/dsp low level device drivers are available for interfacing to the adf7020-1, the adi aduc84x microcontroller parts, or the blackfin adsp-bf53x dsps using the hardware connections shown in figure 36 and figure 37 . 05669-035 preamble sync word id field data field crc figure 35. typical format of a transmit protocol miso aduc84x adf7020-1 mosi sclock ss p3.7 p3.2/int0 p2.4 p2.5 txrxdata rxclk ce int/lock sread sle p2.6 p2.7 sdata sclk gpio 05669-036 a dc-free preamble pattern is recommended for fsk/ask/ ook demodulation. the recommended preamble pattern is a dc-free pattern such as a 10101010 pattern. preamble patterns with longer run-length constraints, such as 11001100, can also be used. however, this results in a longer synchronization time of the received bit stream in the receiver. manchester coding can be used for the entire transmit protocol. however, the remaining fields that follow the preamble header do not have to use dc-free coding. for these fields, the adf7020-1 can accommodate coding schemes with a run- length of up to 6 bits without any performance degradation. figure 36.aduc84x to adf7020-1 connection diagram mosi adsp-bf533 adf7020-1 miso pf5 rsclk1 dt1pri dr1pri rfs1 pf6 sdata sle txrxdata int/lock ce vcc gnd vcc gnd sck sclk sread txrxclk 05669-037 if longer run-length coding must be supported, the adf7020-1 has several other features that can be activated. these involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition. device programming after initial power-up table 12 lists the minimum number of writes needed to set up the adf7020-1 in either tx or rx mode after ce is brought high. additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling afc. when going from tx to rx or vice versa, the user needs to write only to the n register to alter the lo by 200 khz and to toggle the tx/rx bit. figure 37.adsp-bf533 to adf7020-1 connection diagram table 12. minimum register writes required for tx/rx setup mode registers tx reg 0 reg 1 reg 2 rx (ook) reg 0 reg 1 reg 2 reg 4 reg 6 rx (g/fsk) reg 0 reg 1 reg 2 reg 4 reg 6 tx <-> rx reg 0 figure 38 and figure 39 show the recommended programming sequence and associated timing for power-up from standby mode.
adf7020-1 rev. 0 | page 27 of 48 2.0ma 3.65ma 14ma a d f 7 0 2 0 - 1 i d d time reg. ready t 1 wr0 t 2 wr1 t 3 vco t 4 wr3 t 5 wr4 t 6 wr6 t 7 17.6ma to 20.1ma agc/ rssi t 8 cdr t 9 afc t 10 rx data t 11 t off t on _xtal t 0 05669-038 figure 38. rx programming sequence and timing diagram table 13. power-up sequence description parameter value description/notes signal to monitor t0 2 ms crystal starts power-up after ce is brought high. this typically depends on the crystal type and the load capacitance specified. clkout pin t1 10 s time for regulator to power up. the serial interface can be written to after this time. muxout pin t2, t3, t5, t6, t7 32 1/spi_clk time to write to a single register. maximum spi_clk is 25 mhz. t4 1 ms the vco can power-up in parallel with the crystal. this depends on the cvco capacitance value used. a value of 22 nf is recommended as a trade-off between phase noise performance and power-up time. cvco pin t8 150 s this depends on the number of gain changes the agc loop needs to cycle through and agc settings programmed. th is is described in more detail in the agc information and timing section. analog rssi on test_a pin (available by writing 0x3800 000c) t9 5 bit_period this is the time for the clock and data recovery circuit to settle. this typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. t10 16 bit_period this is the time for the automatic frequency control circuit to settle. this typically requires 16-bit transitions to acquire lock and is usually covered by an appropriate length preamble. t11 packet length number of bits in payload by the bit period.
adf7020-1 rev. 0 | page 28 of 48 2.0ma 3.65ma 14ma a d f 7 0 2 0 - 1 i d d time reg. ready t 1 wr0 t 2 wr1 t 3 xtal + vco t 4 wr2 t 5 15ma to 30ma txdata t 12 t off t on 05669-039 figure 39. tx programming sequence and timing diagram
adf7020-1 rev. 0 | page 29 of 48 serial interface the serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (sclk, sdata, and sle). it consists of a voltage level shifter, a 32-bit shift register, and 11 latches. signals should be cmos compatible. the serial interface is powered by the regulator and therefore is inactive when ce is low. data is clocked into the register msb first on the rising edge of each clock (sclk). data is transferred to one of the 11 latches on the rising edge of sle. the destination latch is determined by the value of the four control bits (c4 to c1). these are the bottom 4 lsb, db3 to db0, as shown in the timing diagram in figure 2 . data can also be read back on the sread pin. readback format the readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (r7_db8 = 1). the readback can begin after the control word has been latched with the sle signal. sle must be kept high while the data is read out. each active edge at the sclk pin clocks the readback word out successively at the sread pin, as shown in figure 3 , starting with the msb first. the data appearing at the first clock cycle following the latch operation must be ignored. afc readback the afc readback is valid only during the reception of fsk signals with either the linear or correlator demodulator active. the afc readback value is formatted as a signed 16-bit integer comprised of bits rv1 to rv16 and is scaled according to the following formula: freq_rb [hz] = ( afc_readback demod_clk )/2 15 in the absence of frequency errors, the freq_rb value is equal to the if frequency of 200 khz. note that the down-converted input signal must not fall outside the bandwidth of the analogue if filter for the afc readback to yield a valid result. at low- input signal levels, the variation in the readback value can be improved by averaging. rssi readback the rssi readback operation yields valid results in rx mode with ask or fsk signals. the format of the readback word is shown in figure 40 . it is comprised of the rssi level informa- tion (bits rv1 to rv7), the current filter gain (fg1, fg2), and the current lna gain (lg1, lg2) setting. the filter and lna gain are coded in accordance with the definitions in register 9. with the reception of ask modulated signals, averaging of the measured rssi values improves accuracy. the input power can be calculated from the rssi readback value as outlined in the rssi/agc . battery voltage adcin/temperature sensor readback the battery voltage is measured at pin vdd4. the readback information is contained in bits rv1 to rv7. this also applies for the readback of the voltage at the adcin pin and the temperature sensor. from the readback information, the battery or adcin voltage can be determined using v battery = ( battery_voltage_readback )/21.1 v adcin = ( adcin_voltage_readback )/42.1 silicon revision readback the silicon revision readback word is valid without setting any other registers, especially directly after power-up. the silicon revision word is coded with four quartets in bcd format. the product code (pc) is coded with three quartets extending from bits rv5 to rv16. the revision code (rv) is coded with one quartet extending from bits rv1 to rv4. the product code for the adf7020-1 should read back as pc = 0x200. the current revision code should read back as rc = 0x6. filter calibration readback the filter calibration readback word is contained in bits rv1 to rv8 and is for diagnostic purposes only. using the automatic filter calibration function, accessible through register 6, is recommended. before filter calibration is initiated decimal 32 should be read back. 05669-040 readback mode afc readback db15 rv16 x x rv16 0 rssi readback battery voltage/adcin/ temp. sensor readback silicon revision filter cal readback readback value db14 rv15 x x rv15 0 db13 rv14 x x rv14 0 db12 rv13 x x rv13 0 db11 rv12 x x rv12 0 db10 rv11 lg2 x rv11 0 db9 rv10 lg1 x rv10 0 db8 rv9 fg2 x rv9 0 db7 rv8 fg1 x rv8 rv8 db6 rv7 rv7 rv7 rv7 rv7 db5 rv6 rv6 rv6 rv6 rv6 db4 rv5 rv5 rv5 rv5 rv5 db3 rv4 rv4 rv4 rv4 rv4 db2 rv3 rv3 rv3 rv3 rv3 db1 rv2 rv2 rv2 rv2 rv2 db0 rv1 rv1 rv1 rv1 rv1 figure 40. readba ck value table
adf7020-1 rev. 0 | page 30 of 48 register 0n register tr1 transmit/ receive 0 transmit receive 1 m3 m2 m1 muxout 0 regulator ready (default) 0 r d i v i d e r o u t p u t 0 n divider output 0 digital lock detect 1 analog lock detect 1 three-state 1 pll test modes 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - test modes ple1 pll enable 0 pll off 1 pll on 05669-041 n8 n7 n6 n5 n4 n3 n2 n1 n counter divide ratio 03 1 03 2 . . . 1 253 1 254 1 0 0 . . . 1 1 1 0 1 . . . . . . 1 1 1 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 1 1 1 . . . 1 0 0 1 1 . . . . . . 1 0 1 0 1 255 15-bit fractional-n 8-bit integer-n tx/rx pll enable muxout address bits n5 n4 n8 m5 m6 m7 m8 m12 m13 m15 n1 n2 n3 m14 m9 m10 m11 m4 m3 tr1 ple1 m1 m3 m2 c2 (0) c1 (0) c3 (0) c4 (0) m1 m2 n7 n6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 fractional divide ratio 0 1 2 . . . 32764 32765 32766 32767 m15 0 0 0 . . . 1 1 1 1 m14 0 0 0 . . . 1 1 1 1 m13 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 figure 41. notes 1. the tx/rx bit (r0_db27) configures the part in tx or rx mode and also controls the state of the internal tx/rx switch. 2. ) 2 ( 15 -n fractional integer-n r xtal f out + = .
adf7020-1 rev. 0 | page 31 of 48 register 1oscillator/filter register r3 r2 r1 rf r counter divide ratio 0 0 . . . 1 1 2 . . . 7 1 0 . . . 1 0 1 . . . 1 x1 xtal osc 0 off 1on va2 va1 frequency of operation 0 850?920 0 860?930 1 870?940 1 0 1 0 1 880?950 d1 xtal doubler 0 disable enabled 1 v1 vco div-by-2 0 direct output 1 divide-by-2 output cp2 cp1 rset i cp (ma) 3.6k 0 0 0.3 0 1 0.9 1 0 1.5 1 1 2.1 vb4 vb3 vb2 vb1 vco bias current 0 0.375ma 0 0.625ma . 1 1 0 . 1 0 1 . 1 0 0 . 1 3.875ma ir2 ir1 filter bandwidth 0 100khz 0 150khz 1 200khz 1 0 1 0 1 not used cl4 cl3 cl2 cl1 clk out divide ratio 0 off 0 0 . . . 1 0 1 0 . . . 1 2 4 . . . 0 0 1 . . . 1 0 0 0 . . . 1 30 vco bias cp current vco band xosc enable clockout divide address bits r counter xtal doubler vco adjust if filter bw ir2 ir1 cl1 cl2 cl3 cl4 dd2 vb1 vb3 vb4 va1 va2 vb2 x1 v1 dd1 d1 r3 c2 (0) c1 (1) c3 (0) c4 (0) r1 r2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db1 db0 db2 db3 05669-042 figure 42. notes 1. set the vco adjust bits r1_db (20:21) to 0 for normal operation. 2. see table 5 for the recommended vco bias settings. 3. the divide-by-2 block is enabled by setting r1_db13. as this divide block is outside the pll loop, users must program an n-valu e that corresponds to twice the divide-by-2 output frequency. the deviation frequency is also halved when divide-by-2 is enabled.
adf7020-1 rev. 0 | page 32 of 48 register 2transmit modulati on register (ask/ook mode) p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output high level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm d6 x 0 0 0 0 . . 1 . . . . . . . . . d5 x x 0 0 . . . 1 d2 x x 0 0 1 . . 1 d1 x x 0 1 0 . . 1 power amplifier output low level ook mode pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm di1 0 1 txdata txdata modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5 a 7 a 9 a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 05669-043 d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2 (1) c1 (0) c3 (0) c4 (0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 figure 43. notes 1. figure 13 shows how the pa bias affects the power amplifier level. the default level is 9 a. if you need maximum power, program this value to 11 a. 2. in ask/ook, manchester encoding is recommended to keep the data run length limit to 2 bits. see the ask/ook operation section for more details on dealing with longer run lengths. 3. d7, d8, and d9 are dont care bits.
adf7020-1 rev. 0 | page 33 of 48 register 2transmit modulation register (fsk mode) modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2 (1) c1 (0) c3 (0) c4 (0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 di1 0 1 txdata txdata pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5 a 7 a 9 a 11 a ic2 x ic1 x mc3 x mc2 x mc1 x d9 0 0 0 0 . 1 d3 0 0 0 0 . 1 .... .... .... .... .... .... .... d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 for fsk mode, f deviation pll mode 1 f step 2 f step 3 f step . 511 f step p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 05669-044 figure 44. notes 1. f step = pfd /2 14 . 2. pa bias default = 9 a.
adf7020-1 rev. 0 | page 34 of 48 register 2transmit modulation register (gfsk/gook mode) modulation parameter power amplifier gfsk mod control index counter txdata invert pa bias modulation scheme address bits pa enable mute pa until lock d9 d8 mc3 s3 p1 p2 p3 d1 d2 d4 d5 d6 d7 d3 p4 p5 p6 s2 s1 ic1 ic2 di1 pa2 pa1 c2 (1) c1 (0) c3 (0) c4 (0) pe1 mp1 mc2 mc1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 di1 0 1 txdata txdata pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5 a 7 a 9 a 11 a ic2 0 0 1 1 ic1 0 1 0 1 index_counter 16 32 64 128 d9 0 0 1 1 d8 0 1 0 1 gaussian ? ook mode normal mode output buffer on bleed current on bleed/buffer on 05669-045 mc3 0 0 . 1 mc2 0 0 . 1 gfsk_mod_control 0 1 . 7 mc1 0 1 . 1 d7 0 0 0 0 . 1 d3 0 0 0 0 . 1 ... ... ... ... ... ... ... d2 0 0 1 1 . 1 d1 0 1 0 1 . 1 divider_factor invalid 1 2 3 . 127 pe1 0 1 power amplifier off on mp1 0 1 mute pa until lock detect high off on s3 0 0 0 0 1 s2 0 0 1 1 1 modulation scheme fsk gfsk ask ook gook s1 0 1 0 1 1 p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 x 0 0 1 . . 1 p1 x 0 1 0 . . 1 power amplifier output level pa off ?16.0dbm ?16 + 0.45dbm ?16 + 0.90dbm . . 13dbm figure 45. notes 1. gfsk_deviation = (2 gfsk_mod_control pfd )/2 12 . 2. data rate = pfd /( index_counter divider_factor ). 3. pa bias default = 9 a.
adf7020-1 rev. 0 | page 35 of 48 register 3receiver clock register fs8 0 0 . 1 1 fs7 0 0 . 1 1 fs3 0 0 . 1 1 ... ... ... ... ... ... fs2 0 1 . 1 1 fs1 1 0 . 0 1 cdr_clk_divide 1 2 . 254 255 bk2 0 0 1 bk1 0 1 x bbos_clk_divide 4 8 16 sk8 0 0 . 1 1 sk7 0 0 . 1 1 sk3 0 0 . 1 1 ... ... ... ... ... ... sk2 0 1 . 1 1 sk1 1 0 . 0 1 seq_clk_divide 1 2 . 254 255 ok2 0 0 1 1 ok1 0 1 0 1 demod_clk_divide 4 1 2 3 sequencer clock divide cdr clock divide bb offset clock divide demod clock divide address bits sk8 sk7 fs1 fs2 fs3 fs4 fs8 sk1 sk3 sk4 sk5 sk6 sk2 fs5 fs6 fs7 ok2 ok1 c2(1) c1(1) c3(0) c4(0) bk1 bk2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db1 db0 db2 db3 05669-046 figure 46. notes 1. baseband offset clock frequency (bbos_clk) must be greater than 1 mhz and less than 2 mhz, where divide clkbbos xtal clkbbos __ _ = . 2. the demodulator clock (demod_clk) must be <12 mhz for fsk and <6 mhz for ask, where divide clk demod xtal clk demod __ _ = . 3. data/clock recovery frequency (cdr_clk) should be within 2% of (32 data rate), where divide clkcdr clk demod clkcdr __ _ _ = . note that this might affect your choice of xtal, depending on the desired data rate. 4. the sequencer clock (seq_clk) supplies the clock to the digital receive block. it should be close to 100 khz for fsk and close to 40 khz for ask: divide clkseq xtal clkseq __ _ = .
adf7020-1 rev. 0 | page 36 of 48 register 4demodulator set-up register demodulator lock setting postdemodulator bw demod select demod lock/ sync word match address bits dl8 dl7 dw3 dw4 dw5 dw6 dw10 dl1 dl3 dl4 dl5 dl6 dl2 dw7 dw8 dw9 dw2 dw1 c2(0) c1(0) c3(1) c4(0) ds1 ds2 lm2 lm1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ds2 0 0 1 1 ds1 0 1 0 1 demodulator type linear demodulator correlator/demodulator ask/ook invalid lm2 0 0 0 0 1 1 demod mode 0 1 2 3 4 5 lm1 0 0 1 1 0 1 demod lock/sync word match serial port control?free running serial port control?lock threshold sync word detect?free running sync word detect?lock threshold interrupt/lock pin locks threshold demod locked after dl8?dl1 bits int/lock pin ? ? output output input ? dl8 0 1 0 1 x dl8 dl7 0 0 0 . 1 1 dl8 0 0 0 . 1 1 dl3 0 0 0 . 1 1 ... ... ... ... ... ... ... dl2 0 0 1 . 1 1 dl1 0 1 0 . 0 1 lock_threshold_timeout 0 1 2 . 254 255 05669-047 mode5 only figure 47. notes 1. demodulator modes 1, 3, 4, and 5 are modes that can be activated to allow the adf7020-1 to demodulate data-encoding schemes that have run-length constraints greater than 7. 2. post_demod_bw = 2 11 f cutoff / demod_clk , where the cutoff frequency ( f cutoff ) of the postdemodulator filter should typically be 0.75 times the data rate. 3. for mode 5, the timeout delay to lock threshold = ( lock_threshold_setting )/ seq_clk , where seq_clk is defined in the register 3receiver clock register section.
adf7020-1 rev. 0 | page 37 of 48 register 5sync byte register pl2 0 0 1 1 pl1 0 1 0 1 sync byte length 12 bits 16 bits 20 bits 24 bits mt2 0 0 1 1 mt1 0 1 0 1 matching tolerance 0 errors 1 error 2 errors 3 errors sync byte sequence control bits sync byte length matching tolerance mt2 mt1 c2(0) c1(1) c3(1) c4(0) pl1 pl2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 05669-048 figure 48. notes 1. sync byte detect is enabled by programming bits r4_db (25:23) to [010] or [011]. 2. this register allows a 24-bit sync byte sequence to be stored in ternally. if the sync byte detect mode is selected, the int/loc k pin goes high when the sync byte is detected in rx mode. once the sy nc word detect signal goes high, it goes low again after nine d ata bits. 3. the transmitter must transmit the msb of the sync byte first and the lsb last to ensure proper alignment in the receiver sync b yte detection hardware. 4. choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s.
adf7020-1 rev. 0 | page 38 of 48 register 6correlator/demodulator register demod reset cdr reset discriminator bw if filter divider lna current lna mode dot product rxdata invert if filter cal mixer linearity rx reset address bits fc4 fc3 fc7 td5 td6 td7 td8 lg1 li1 ml1 ca1 fc1 fc2 li2 td9 td10 dp1 td4 td3 fc8 fc9 ri1 c2(1) c1(0) c3(1) c4(0) td1 td2 fc6 fc5 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ri1 0 1 rxdata invert rxdata rxdata ca1 0 1 filter cal no cal calibrate ml1 0 1 mixer linearity default high dp1 0 1 dot product cross product dot product lg1 0 1 lna mode default reduced gain fc3 0 0 . . . . 1 fc1 1 0 . . . . 1 filter clock divide ratio 1 2 . . . . 511 fc2 0 1 . . . . 1 fc9 0 0 . . . . 1 fc6 0 0 . . . . 1 . . . . . . . . fc5 0 0 . . . . 1 fc4 0 0 . . . . 1 li2 0 li1 0 lna bias 800 a (default) 05669-049 figure 49. notes 1. see the fsk correlator/demodulator section for an example of how to determine register settings. 2. nonadherence to correlator programming guidelines results in poorer sensitivity. 3. the filter clock is used to calibrate the if filter. the filter clock divide ratio should be adjusted so that the frequency is 50 khz. the formula is xtal/filter_clock_divide. 4. the filter should be calibrated only when the crystal oscillator is settled. the filter calibration is initiated every time bit r6_db19 is set high. 5. discriminator_bw = ( demod_clk k )/(800 10 3 ). see the fsk correlator/demodulator section. maximum value = 600. 6. when lna mode = 1 (reduced gain mode), this prevents the rx from selecting the highest lna gain setting. this might be used when linearity is a concern. see table 6 for details of the rx modes.
adf7020-1 rev. 0 | page 39 of 48 register 7readback set-up register ad1 ad2 rb1 rb2 rb3 db8 db7 db6 db5 db4 db3 db2 c2(1) c1(1) control bits db1 db0 c3(1) c4(0) readback select adc mode ad2 0 0 1 1 ad1 0 1 0 1 adc mode measure rssi battery voltage temp sensor to external pin rb2 0 0 1 1 rb1 0 1 0 1 readback mode afc word adc output filter cal silicon rev rb3 0 1 readback disabled enabled 05669-050 figure 50. notes 1. readback of the measured rssi value is valid only in rx mode. to enable readback of the battery voltage, the temperature sensor , or the voltage at the external pin in rx mode, users must disable the agc function in register 9. to read back these parameters in tx mode, users must first power up the adc using register 8, because it is off by default in tx mode to save power. this is the recommended method of using the battery readback function since most configurations typically require use of the agc function. 2. readback of the afc word is valid in rx mode only if either the linear demodulator or the correlator/demodulator is active. 3. see the readback format section for more information.
adf7020-1 rev. 0 | page 40 of 48 register 8power-down test register pd1 pd2 pd3 pd4 pd5 db8 db7 db6 db5 db4 db3 db2 c2(0) c1(0) control bits db1 db0 c3(0) c4(1) log amp/ rssi synth enable vco enable lna/mixer enable filter enable adc enable demod enable internal tx/rx switch enable pa enable rx mode pd7 db15 db14 db13 db12 db11 lr1 pd6 db10 db9 lr2 sw1 pd7 0 1 pa (rx mode) pa off pa on sw1 0 1 tx/rx switch default (on) off pd6 0 1 demod enable demod off demod on pd5 0 1 adc enable adc off adc on lr2 x x lr1 0 1 rssi mode rssi off rssi on pd4 0 1 filter enable filter off filter on pd3 0 1 lna/mixer enable lna/mixer off lna/mixer on ple1 (from reg 0) 0 0 0 0 1 pd2 0 0 1 1 x loop condition vco/pll off pll on vco on pll/vco on pll/vco on pd1 0 1 0 1 x 05669-051 figure 51. notes 1. for a combined lna/pa matching network, bit r8_db12 should al ways be set to 0. this is the power-up default condition. 2. it is not necessary to write to this register under normal operating conditions.
adf7020-1 rev. 0 | page 41 of 48 register 9agc register agc high threshold lna gain filter gain digital test iq agc search gain control filter current agc low threshold address bits fg2 fg1 gl5 gl6 gl7 gh1 gh5 gh6 gs1 gc1 lg1 lg2 gh7 gh2 gh3 gh4 gl4 gl3 c2(0) c1(1) c3(0) c4(1) gl1 gl2 fi1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 fi1 0 1 filter current low high gs1 0 1 agc search auto agc hold setting gc1 0 1 gain control auto user fg2 0 0 1 1 fg1 0 1 0 1 filter gain 8 24 72 invalid lg2 0 0 1 1 lg1 0 1 0 1 lna gain <1 3 10 30 gl3 0 0 0 1 . . . 1 1 1 gl1 1 0 1 0 . . . 1 0 1 agc low threshold 1 2 3 4 . . . 61 62 63 gl2 0 1 1 0 . . . 0 1 1 gl7 0 0 0 0 . . . 1 1 1 gl6 0 0 0 0 . . . 1 1 1 gl5 0 0 0 0 . . . 1 1 1 gl4 0 0 0 0 . . . 1 1 1 gh3 0 0 0 1 . . . 1 1 0 gh1 1 0 1 0 . . . 0 1 0 rssi level code 1 2 3 4 . . . 78 79 80 gh2 0 1 1 0 . . . 1 1 0 gh7 0 0 0 0 . . . 1 1 1 gh6 0 0 0 0 . . . 0 0 0 gh5 0 0 0 0 . . . 0 0 1 gh4 0 0 0 0 . . . 1 1 0 05669-052 figure 52. notes 1. default agc_low_threshold = 30, default agc_high_threshold = 70. see the rssi/agc for details. 2. agc high and low settings must be more than 30 settings apart to ensure correct operation. 3. lna gain of 30 is available only if the lna mode bit, r6_db15, is set to 0.
adf7020-1 rev. 0 | page 42 of 48 register 10agc 2 register agc delay i/q gain adjust leak factor i/q phase adjust up/down reserved select i/q select i/q peak response address bits r1 siq1 ph3 gl4 gl5 gl6 gl7 dh4 gc1 gc3 gc4 gc5 ud1 gc2 dh1 dh2 dh3 pr4 pr3 ph4 siq2 c2 (1) c1 (0) c3 (0) c4 (1) pr1 pr2 ph2 ph1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 siq2 0 1 select iq phase to i channel phase to q channel siq2 0 1 select iq gain to i channel gain to q channel default = 0xa default = 0x2 default = 0xa 05669-053 figure 53. notes 1. this register is not used under normal operating conditions. register 11afc register afc scaling coefficient control bits afc enable m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m16 ae1 m3 c2(1) c1(0) c3(0) c4(0) m1 m2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ae1 0 1 internal afc off on 05669-054 figure 54. notes 1. see the internal afc section to program afc scaling coefficient bits. 2. the afc scaling coefficient bits can be programmed using the following formula: afc_scaling_coefficient = round ((500 2 24 )/ xtal ).
adf7020-1 rev. 0 | page 43 of 48 register 12test register counter reset digital test modes - test modes analog test mux image filter adjust osc test force ld high source prescaler pll test modes address bits sf6 sf5 t5 t6 t7 t8 sf1 sf2 sf3 sf4 t9 t4 t3 pre c2(0) c1(0) c3(1) c4(1) t1 t2 qt1 cs1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 p 0 1 prescaler 4/5 (default) 8/9 cr1 0 1 counter reset default reset cs1 0 1 cal source internal serial if bw cal default = 32. increase number to increase bw if user cal on 05669-055 figure 55. using the test dac on the adf7020-1 to implement analog fm demodulation and measuring of snr the test dac allows the output of the postdemodulator filter for both the linear and correlator/demodulators ( figure 31 and figure 32 ) to be viewed externally. it takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback - converter. the output can be viewed on the clkout pin. this signal, when if filtered appropriately, can then be used to ? monitor the signals at the fs k/ask postdemodulator filter output. this allows the demodulator output snr to be measured. eye diagra ms can also be constructed of the received bit stream to measure the received signal quality. ? provide analog fm demodulation. while the correlators and filters are clocked by demod_clk, cdr_clk clocks the test dac. note that, although the test dac functions in a regular user mode, the best performance is achieved when the cdr_clk is increased up to or above the frequency of demod_clk. the cdr block does not function when this condition exists. programming the test register, register 12, enables the test dac. in correlator mode, this can be done by writing digital test mode 7 or 0x0001c00c. to view the test dac output when using the linear demodulator, the user must remove a fixed offset term from the signal using register 13. this offset is nominally equal to the if frequency. the user can determine the value to program by using the frequency error readback to determine the actual if and then programming half this value into the offset removal field. it also has a signal gain term to allow the usage of the maximum dynamic range of the dac. setting up the test dac ? digital test modes = 7: enables the test dac, with no offset removal (0x0001 c00c). ? digital test modes = 10: enables the test dac, with offset removal (needed for linear demod only, 0x02 800c). the output of the active demodulator drives the dac; that is, if the fsk correlator/demodulator is selected, the correlator filter output drives the dac.
adf7020-1 rev. 0 | page 44 of 48 register 13offset removal and signal gain register kp ki control bits pulse extension test dac gain test dac offset removal pe1 pe2 pe3 pe4 c2(0) c1(1) c3(1) c4(1) db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 pe4 0 0 0 . . . 1 pe3 0 0 0 . . . 1 pe2 0 0 1 . . . 1 pulse extension normal pulse width 2 pulse width 3 pulse width . . . 16 pulse width pe1 0 1 0 . . . 1 05669-056 figure 56. notes 1. because the linear demodulators output is proportional to frequency, it usually consists of an offset combined with a relative ly low signal. up to a maximum of a 300 khz offset can be removed and gained to use the full dynamic range of the dac: dac_input = (2 test_dac_gain ) ( signal ? test_dac_offset_removal /4096).
adf7020-1 rev. 0 | page 45 of 48 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 4.25 4.10 sq 3.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicato r coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 57. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-3) dimensions shown in millimeters ordering guide model temperature range package description package option adf7020-1bcpz 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 adf7020-1bcpz-rl 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 adf7020-1bcpz-rl7 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 eval-adf70xxmb control mother board eval-adf70xxmb2 evaluation platform eval-adf7020-1db4 400 mhz to 435 mhz daughter board eval-adf7020-1db5 135 mhz to 650 mhz daughter board 1 z = pb-free part.
adf7020-1 rev. 0 | page 46 of 48 notes
adf7020-1 rev. 0 | page 47 of 48 notes
adf7020-1 rev. 0 | page 48 of 48 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05669C0C12/05(0)

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